Yub pa PCBA caku ku Maku cal, ma lubo ku Kethu PCB, Routing, DRC (Design Rule Check), man DFM Check, man ewok Gerber Files, NC Drill Files, BOM (Bill of Materials), man Cal mi coko. Pi yub ma tek, HDI PCB diro ku laser-drilled microvias man lamination ma lubo copo bedu piny ma mitere.

Lembe ma pire tek uketho i iye:

• Netlist
• Goyo cal ku cuma
• Karatasi mi lembe pa piny
• Karatasi mi kero mi tic (lac/kabedo ma nok, dit pa vur ma nok, lat pa dam mi solder mask, piny ma mitere pi jwigo impedance)

Core output files uketho i iye:

• Gerber RS-274X nyo ODB++
• NC Drill File
• Yer & Keth fail
• Stencil Gerber
• Lapor pa lembe ma jutimo
• Cal ma jucoko & Silkscreen File

2.1 Cik mi ketho kabedo

Kethu piny ubedo the cen pa yub pa PCBA man edoko piny Ber pa cwalo lanyuth, Tic mi lyethu, man Yubu piny. Kethu piny maber piretek pi impedance control PCB yiku man jam tic ma rwom pare malu.

• Poko tic: Pok kabedo mi analog, digital, power, man high-speed interface kara kud ibed ku peko.
• Woth pa lanyuth: Keth piny moko i yo ma rwom pa lanyuth mol kudu pi jwigo kabedo mi kadho man loop.
• Piny ma pire tek ma pire tek: Keth MCU/FPGA/SoC, DDR, sawa, man jam kero ma kwong.
• Kabedo mi ngete: Jam mako, buttons, man LEDs ceng ku ngete pa board pi rombu ku yeny pa cuma.
• Thermal Layout: Jam tic ma tek tek ceng ku yore mi wodhu lyethu nyo thermal pads; medi lyethu nikadhu kud i arrays ithe piny ma lyeth.

2.2 Routing Essentials

• Lub Lac & Ker ma kawoni: 0.5 mm lac pa 1 oz copper tingo 1 A. Pi kero ma malu, ti ku copper pi nyo pek pa copper ma gwai.
• Differential Pair: USB, HDMI, LVDS, Ethernet mitu Bor ma rwate, Kabedo marom, man Coupling ma tek ni gwoko bedo maleng pa lanyuth man dwoko piny rweny pa ketho man dwoko piny ma rwinyo.
• Impedance ma jugwoko: Signals ma ngweje tek mitu impedance ma jukwanu kud i stack-up; wel ma rom utiye 50 Ω acel acel man 100 Ω tung tung. Neno pa engineering umaku obed ku impedance control ketho lembe.
• Yo mi dwogo: Bed ku nen pa reference plane ma pong kara kud ibed ku peko mi Split plane EMI; medi yore mi tweyo kago ku aloka loka pa dul.
• Yor: Keth yore mi ngwec ma tek piny; tiyo kude Turo ngeye nyo Vias ma wange otho/juyiko ka mitire. Pi HDI designs, ti ku stacked vias nyo vias ma ucungo ku pong pa copper.

DFM marac tero ni Solder Bridging, Goyo kidi i liel, Cold Solder Joints, Lokruok pa piny, man Solder Balls. DFM analysis ma podi juyubu ngo madwong konyo ni gwoko wel ma juyubu ma kwong.

3.1 Yub pa ngom

Kit ngom umaku ulub IPC-7351. Yub pa pad maber piretek pi bedo maber PCB assembly man PCBA assembly.

• CHIP Components (0402, 0603, 0805): Dit pa pad umaku urombo ku stencil aperture man reflow profile mi gwoko tombstoning.
• QFN (Quad Flat No-lead): piny Thermal Pad umitu jupoke pi jwigo pii man ngico; tiyo kude solder mask defined (SMD) nyo non-solder mask defined (NSMD) pads maber.
• BGA (Ball Grid Array): Lat pa pad ubedo 80-85% pa lat pa mupira; yabo mask mi solder umaku obed maleng pi gwoko solder mask ikum pad. Pi BGA maber, ti ku solder mask dam lac ≤0.1 mm nyo kwany dam ka mitire.
• SOT/SOP/QFP: Fine pitch mito solder mask dam width ma romo pi juku bridging.

3.2 Poko piny man nen pa piny

• Kabedo pa piny ma ceng kudu umaku urombo ku yeny pa pick-and-place nozzle man rework (≥0.3 mm).
• Keth piny marom rom i yo acel pi neno AOI mayot.
• Keth bor ma romo ikind piny ma bor ku ma nok kara kud ibed ku tipo i saa mi reflow.

3.3 Solder Mask & Silkscreen

• Solder Mask Dam lac ≥0.1 mm mi juku rwinyo.
• Silkscreen umitu kud ucung ikum pads; gwoko ≥0.2 mm mabor.
• Polarity Marking, Pin 1 lanyuth, man Jatel wi lembe umitu obed maleng.
• Yer rangi pa solder mask (macol, macol, macol, makwar, tar) nimakere ku paru pa juruwil; nen nia lembe ma jugoro ubedo yot.

4.1 DFT

DFT konyowa ni timo test mi PCBA maber man ma wel pare lapiny man ekonyo yubu program mi test man yubu piny.

• Temo Flying Probe: Piny moko mbe ma mitere; ber pi prototypes man batch ma nok.
• ICT (In-Circuit Test): Mitu kabedo mi pimo man piny ma juciko; ber pi dwand ma malu. Wayubu kite mi temo ku rwom ma oromo.
• FCT (Functional Circuit Test): Nyuthu tic pa PCBA mandha.
• Boundary Scan (JTAG): Tiyu ku chip test logic ma juketho i iye pi jwigo piny ma jutimo.

DFT ma mitere:

• Kabedo mi pimo diameter ≥0.8 mm, spacing ≥1.27 mm.
• Pok kabedo mi pimo i thenge acel ka copu bedu.
• Keth kabedo mi pimo piny maber man bor ku piny mabor.
• Gwok kabedo mi pimo pi kero man ground nets kara etim tic temo ma nok mi ketho teko man pimo kero pa mac.

4.2 DFA

DFA ketho cwinye ikum tic maber pa coko man gwoko peko.

• Panelization: Tiyo kude V-cut (V-Scoring) nyo Mouse Bite / Stamp Hole. Kum pcb assembly ku piny ma ucungo iwi ngete, ti ku tab routing ku kac pa oyo.
• Tooling Rail: 3-5 mm lac pi tero piny man ketho piny.
• Fiducial Mark: Ma nok 2-3 fiducials mi ng'om zoo; fiducials mi kabedo pi jam tic maber calu BGA man QFN.
• Poka-Yoke: Nenu nia jam mako gi bedu ku yore migi ma ukoc pi juku dwoko piny.

5.1 Bedo pa lanyuth (SI)

Lembe pa SI uketho i iye Lwodho, Crosstalk, Overshoot, Undershoot, man Timing Skew. Ngwec matek Yub pa PCB copo tiyo ku labol ma podi juyubu ngo man ngiyo i ngei layout ni pimo cal pa wang.

• Impedance Matching: Source series termination, parallel termination, nyo AC termination.
• Bor ma rwate: Serpentine routing pi DDR data/address groups man differential pairs.
• Crosstalk Suppression: 3W rule (spacing ≥3× trace width); med lanyuth pa gwoko pi lanyuth ma pire tek.
• Dwogo kud i: Med stitching vias ceng ku layer transitions mi jwigo loop inductance.

5.2 Ker pa teko (PI)

Lembe pa PI uketho i iye Woy pa teko, Voltage Drop, man Ground Bounce. Ma juyike maber Kabedo mi poko mac (PDN) piretek pi tic maber.

• Decoupling Capacitor: Keth 0.1 μF + 10 μF karacelu ceng ku piny acel acel; tiyo kude low-ESL capacitors pi high-frequency decoupling.
• Power Plane Split: Pok analog ku digital power planes; kud i kadho i kabedo ma tung tung ku lanyuth ma tek.
• Yore mi impedance ma piny: Kero man piny ma ceng kudu gi cwio capacitance mi ndege; gwoko dielectric ma nyap ikind kero man ngom.
• Ni kadhu kud i kwan: Parallel multiple vias for high-current paths; tiyo kude copper-filled vias pi vias ma rwom pare malu.

5.3 EMC (Electromagnetic Compatibility)

EMC umu EMI (Electromagnetic Interference) man EMS (Electromagnetic Susceptibility). EMC pre-compliance review copo nyutho peko mi design mapodi jutimo ngo test.

• Cik pa 20H: Recess power plane edges by 20× layer spacing to reduce fringing fields.
• Filtering mi interface: Med TVS, common mode chokes, ferrite beads, man capacitors i I/O connectors.
• Gwok: Ti ku jam gwoko kum iwi kabedu ma nyai; miko grounding pads pi mako shield.
• Crystal & Clock: Routing epe piny pa crystals; ti ku lanyuth pa gwoko man iket lanyuth pa sawa ma nok.

5.4 HDI PCB Design

Pi yub ma dit, HDI PCB diro ku laser-drilled microvias, vias ma wange otho, man vias ma juyiko ketho form factors ma nok man routing density ma malu. Lembe ma pire tek:

• Microvia aspect ratio pol kare ≤1:1.
• Tiyo kude microvias ma jukubotho pi loko dul i kabedu ma dhanu dwong iye.
• Lamination ma lubo yub weko microvia layers madwong.
• Via-in-pad ku pong pa copper man planarization pi BGA fanout.

6.1 BGA Design

BGA pad design loko rwom pa soldering pi PCB assembly man PCBA assembly, asaga in tic pa BGA maber.

• Pad diameter ≈0.8–0.85× ball diameter (e.g., 0.25 mm pad pi 0.3 mm ball).
• Solder mask ma oyabe malac uloyu pad ku 0.025-0.05 mm ku thenge acel acel.
• NSMD (Non-Solder Mask Defined) nyo SMD (Solder Mask Defined); NSMD ma rwinyo pi BGA maber.
• Fanout vias 0.2 mm/0.1 mm nyo ma nok; tiyo kude Via-in-Pad ku Copper Filled / Resin Filled mi juku solder wicking.
• Medi lanyuth mi kabedo kago ku BGA pi ketho piny maber.

6.2 QFN Design

QFN (Quad Flat No-lead) packages mito yub maber pa thermal pad.

• Pok thermal pad i pads ma nok nok nyo ti ku pad acel ku stencil apertures ma jupoko pi jwigo pii.
• Med pin pads 0.2-0.3 mm ikum ngete pa jeni pi neno AOI.
• Tiyo kude Resin Plugging nyo Copper Filling pi thermal pad vias mi juku solder wicking.
• Pi QFN ma tek, med lyethu nikadhu kud i array mako ku copper planes ma iye.

6.3 0402 / 0201 / 01005 Micro Components

• 0402 pad spacing: 0.4–0.5 mm; 0201: 0.25–0.3 mm; 01005: 0.15–0.2 mm.
• Ti ku anti-solder ball stencil apertures (ma jugoro nyo judwoko piny).
• Mi lanyuth ma romo pi bedo maber pa kabedo.
• Kethi iparo peri poko glue pi ketho piny ario ku piny ma pek.

7.1 Stencil Aperture Design

Yub pa stencil aperture lokore goyo piny ber man umaku juyike pi PCBA acel acel.

• Lat pa stencil: 0.1–0.15 mm ma rwinyo; 0.08 mm pi piny ma nok nok; 0.2 mm pi kero ma malo.
• Ratio pa kabedo: Aperture area / aperture wall area > 0.66.
• Aspect Ratio: Aperture width / stencil thickness > 1.5.
• Apertures ma pire tek: QFN thermal pad multiple small windows; BGA circular nyo square reduction; anti-solder ball notched apertures for chip components.
• Kethi iparo peri step stencil pi dit pa piny matung tung (e.g., stencil ma gwai pi kabedo ma rwom pare tek, ma nyap pi rwom ma piny).

7.2 Reflow & Wave Soldering

• Reflow Soldering: Pi SMT components; mito ber kite mi lyethu (lyeyo, lwoko, dwoko piny, lyel). Tiyo kude dwoko pa nitrogen pi bero pa pii man dwoko piny pa oxidation.
• Wave Soldering: Pi through-hole (DIP) components man SMT red glue process.
• Selective Wave Soldering: Localized soldering for through-hole components; ber pi mixed-technology boards.
• Yore ma epe ku lead: SAC305 solder paste; lyethu ma malu 235-250 °C. Kit ma piny nen kudu uketho i iye HASL ma epe ku lead, AYIYO, Jurutic mi juku mac, fedha mi pii, man tin mi pii.

7.3 Coko matung tung

Med SMT reflow ku DIP wave soldering, nyo ti ku Pin-in-Paste (PIP) pi jam piny ma wok kud i vur i reflow.

8.1 Yore mi poko lembe

• V-cut (V-Scoring): Bei ma piny; pi board ma nen calu rectangular ma epe ku thenge.
• Mouse Bite / Stamp Hole: Pi boards ma rwinyo ngo nyo piny ma rwinyo; tiyo kude tab routing ku camo pa oyo.
• Bridge + Mouse Bite: Kethu tego man yot pa poko.

8.2 Tooling Rail & Fiducial Mark

• Lat pa jam tic: 3-5 mm.
• Fiducial mark: 1 mm diameter, 2-3 mm solder mask opening, gold or immersion tin finish.
• Local fiducials pi BGA/QFN fine-pitch devices.

8.3 Dit pa panel & wel

• Dit pa panel ikind pick-and-place man reflow oven limits (≤400 mm × 400 mm).
• Bedo ber man tic ku piny; jwigo warpage.
• Tiyo kude breakaway tabs nyo kabedo ma jucwalo mi jwigo peko i saa mi depaneling.

9.1 Nen pa mac

• DRC epe ku lembe ma rac.
• Bor pa lanyuth ma pire tek, impedance, spacing.
• Power net nikadhu kud i wel man kero ma kawoni.
• Lapor pa rwom pa lanyuth adwogi urombo ku yeny pa cal pa wang.

9.2 DFM Check

• Dit pa pad nimakere ku IPC-7351.
• Kabedo pa piny moko romo ku piny ma mitere ma nok.
• Solder mask dam, silkscreen, polarity marking clear.
• Stencil aperture rwate ku area ratio.
• Panelization man jam tic atiye.

9.3 DFT Check

• Tem kabedo mi temo ikum nets ma pire tek.
• Kabedo mi temo unobstructed.
• ICT fixture feasibility.

9.4 Nen coko

• Tooling rail man fiducial marks utiye.
• Yore mi poko lembe ber.
• Bor pa piny ku V-cut ≥0.5 mm.

9.5 Lembe ma jugoro ma oromo

• Gerber layer naming standardized.
• Namba pa BOM, jeni, wel ma atira.
• Kwan man iket fail ma rom ku BOM.
• Karatasi mi stencil urombo ku kit ma juyubu ku PCB.

Pi piny macon nyo macon PCBA circuit boards, PCBA reverse engineering copo dwoko schematics, BOM, man Gerber files kud i physical boards man mako data ma judwoko ni manyen Yub pa PCB man PCBA assembly tic.

Lembe mwa mi dwoko piny ma nyen uketho i iye:

• Cal pa board man neno pa X-ray ni map dul ma iye.
• Nyuthu piny man kwanyo BOM ikinde utiye loko piny ma dong ukadhu.
• Maku cal kud i netlist reconstruction.
• PCB layout recreation ku DFM maber.
• Jam yik pa PCBA man pimo tic.

Tic mukende ma medo ber pa piny:

• Conformal coating pi kabedo ma rac.
• Potting man encapsulation pi juku yeng yeng.
• Pongu piny pi BGA man CSP.
• Tic kendu man yiko tiyo ku BGA rework station.
• Yubu pima ma tiyo pi PCBA ma juyike.